20230329 first commit

.gitignore

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+.DS_Store

lab2/Lab2_alu.v

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+module ALU(
+    alu_out,
+    instruction,
+    inputA,
+    inputB,
+    clk,
+    reset
+);
+
+//==== i/o definition ====
+output [7:0] alu_out;
+input  [7:0] inputA,inputB;
+input  [3:0] instruction;
+input        clk,reset;
+
+//==== reg/wire definition ====
+reg [7:0] alu_out,X,reg_A,reg_B;
+wire [7:0] inputB_inv;
+reg [3:0] reg_ins;
+wire [7:0] sum;
+
+//==== sequential circuit ====
+always@( posedge clk or negedge reset ) begin
+    if(~reset) begin
+        alu_out <= 0;
+        reg_A <= 0;
+        reg_B <= 0;
+        reg_ins <= 0;
+    end
+    else begin
+        alu_out <= X;
+        reg_A <= inputA;
+        reg_B <= inputB;
+        reg_ins <= instruction;
+    end
+end
+
+
+assign inputB_inv = ~reg_B;
+always@( reg_A or reg_B or reg_ins or inputB_inv or sum ) begin 
+    case(reg_ins)
+        4'b0000: X = reg_A+reg_B;    
+        4'b0001: X = reg_A-reg_B;                 
+        4'b0010: X = inputB_inv;            
+        4'b0011: X = reg_A&reg_B;
+        4'b0100: X = reg_A|reg_B;     
+        default: X = reg_A^reg_B;            
+  endcase
+end
+
+endmodule

lab2/Lab2_alu_run.f

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+Lab2_test_alu.v
+Lab2_alu.v

lab2/Lab2_alu_run_s.f

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+Lab2_test_alu.v
+Lab2_alu_s.v
+/home/raid7_2/course/cvsd/CBDK_IC_Contest_v2.5/Verilog/tsmc13_neg.v

lab2/Lab2_alu_s.sdf

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+(DELAYFILE
+(SDFVERSION "OVI 1.0")
+(DESIGN "ALU")
+(DATE "Wed Nov 24 15:00:53 2004")
+(VENDOR "typical")
+(PROGRAM "Synopsys Design Compiler cmos")
+(VERSION "V-2003.12-SP1")
+(DIVIDER /)
+(VOLTAGE 1.80:1.80:1.80)
+(PROCESS)
+(TEMPERATURE 25.00:25.00:25.00)
+(TIMESCALE 1ns)
+(CELL
+  (CELLTYPE "ALU")
+  (INSTANCE)
+  (DELAY
+    (ABSOLUTE
+    (INTERCONNECT U69/Y addsub/U12/A (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_0_/Q addsub/U11/A (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U12/Y addsub/U11/B (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_1_/Q addsub/U10/A (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U12/Y addsub/U10/B (0.000:0.000:0.000))
+    (INTERCONNECT reg_A_reg_0_/Q addsub/U1_0/A (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U11/Y addsub/U1_0/B (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U12/Y addsub/U1_0/CI (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_2_/Q addsub/U9/A (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U12/Y addsub/U9/B (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_3_/Q addsub/U8/A (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U12/Y addsub/U8/B (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_4_/Q addsub/U7/A (0.000:0.000:0.000))
+    (INTERCONNECT U69/Y addsub/U7/B (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_5_/Q addsub/U6/A (0.000:0.000:0.000))
+    (INTERCONNECT U69/Y addsub/U6/B (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_6_/Q addsub/U5/A (0.000:0.000:0.000))
+    (INTERCONNECT U69/Y addsub/U5/B (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_7_/Q addsub/U4/A (0.000:0.000:0.000))
+    (INTERCONNECT U69/Y addsub/U4/B (0.000:0.000:0.000))
+    (INTERCONNECT reg_A_reg_7_/Q addsub/U1_7/A (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U4/Y addsub/U1_7/B (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U1_6/CO addsub/U1_7/C (0.000:0.000:0.000))
+    (INTERCONNECT reg_A_reg_5_/Q addsub/U1_5/A (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U6/Y addsub/U1_5/B (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U1_4/CO addsub/U1_5/CI (0.000:0.000:0.000))
+    (INTERCONNECT reg_A_reg_3_/Q addsub/U1_3/A (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U8/Y addsub/U1_3/B (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U1_2/CO addsub/U1_3/CI (0.000:0.000:0.000))
+    (INTERCONNECT reg_A_reg_1_/Q addsub/U1_1/A (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U10/Y addsub/U1_1/B (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U1_0/CO addsub/U1_1/CI (0.000:0.000:0.000))
+    (INTERCONNECT reg_A_reg_6_/Q addsub/U1_6/A (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U5/Y addsub/U1_6/B (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U1_5/CO addsub/U1_6/CI (0.000:0.000:0.000))
+    (INTERCONNECT reg_A_reg_4_/Q addsub/U1_4/A (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U7/Y addsub/U1_4/B (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U1_3/CO addsub/U1_4/CI (0.000:0.000:0.000))
+    (INTERCONNECT reg_A_reg_2_/Q addsub/U1_2/A (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U9/Y addsub/U1_2/B (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U1_1/CO addsub/U1_2/CI (0.000:0.000:0.000))
+    (INTERCONNECT reg_ins_reg_0_/Q U69/A (0.000:0.000:0.000))
+    (INTERCONNECT U51/Y U69/B (0.000:0.000:0.000))
+    (INTERCONNECT inputB[2] reg_B_reg_2_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_B_reg_2_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U65/Y reg_B_reg_2_/RN (0.000:0.000:0.000))
+    (INTERCONNECT inputB[3] reg_B_reg_3_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_B_reg_3_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U66/Y reg_B_reg_3_/RN (0.000:0.000:0.000))
+    (INTERCONNECT inputB[4] reg_B_reg_4_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_B_reg_4_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U67/Y reg_B_reg_4_/RN (0.000:0.000:0.000))
+    (INTERCONNECT inputB[5] reg_B_reg_5_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_B_reg_5_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U68/Y reg_B_reg_5_/RN (0.000:0.000:0.000))
+    (INTERCONNECT inputB[6] reg_B_reg_6_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_B_reg_6_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U68/Y reg_B_reg_6_/RN (0.000:0.000:0.000))
+    (INTERCONNECT instruction[3] reg_ins_reg_3_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_ins_reg_3_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U66/Y reg_ins_reg_3_/RN (0.000:0.000:0.000))
+    (INTERCONNECT instruction[2] reg_ins_reg_2_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_ins_reg_2_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U65/Y reg_ins_reg_2_/RN (0.000:0.000:0.000))
+    (INTERCONNECT instruction[1] reg_ins_reg_1_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_ins_reg_1_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U64/Y reg_ins_reg_1_/RN (0.000:0.000:0.000))
+    (INTERCONNECT instruction[0] reg_ins_reg_0_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_ins_reg_0_/CK (0.000:0.000:0.000))
+    (INTERCONNECT reset reg_ins_reg_0_/RN (0.000:0.000:0.000))
+    (INTERCONNECT U37/Y alu_out_reg_7_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk alu_out_reg_7_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U67/Y alu_out_reg_7_/RN (0.000:0.000:0.000))
+    (INTERCONNECT U40/Y alu_out_reg_6_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk alu_out_reg_6_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U68/Y alu_out_reg_6_/RN (0.000:0.000:0.000))
+    (INTERCONNECT U33/Y alu_out_reg_5_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk alu_out_reg_5_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U68/Y alu_out_reg_5_/RN (0.000:0.000:0.000))
+    (INTERCONNECT U34/Y alu_out_reg_4_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk alu_out_reg_4_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U67/Y alu_out_reg_4_/RN (0.000:0.000:0.000))
+    (INTERCONNECT inputA[4] reg_A_reg_4_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_A_reg_4_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U67/Y reg_A_reg_4_/RN (0.000:0.000:0.000))
+    (INTERCONNECT U35/Y alu_out_reg_3_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk alu_out_reg_3_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U66/Y alu_out_reg_3_/RN (0.000:0.000:0.000))
+    (INTERCONNECT U36/Y alu_out_reg_2_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk alu_out_reg_2_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U65/Y alu_out_reg_2_/RN (0.000:0.000:0.000))
+    (INTERCONNECT U38/Y alu_out_reg_1_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk alu_out_reg_1_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U64/Y alu_out_reg_1_/RN (0.000:0.000:0.000))
+    (INTERCONNECT U39/Y alu_out_reg_0_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk alu_out_reg_0_/CK (0.000:0.000:0.000))
+    (INTERCONNECT reset alu_out_reg_0_/RN (0.000:0.000:0.000))
+    (INTERCONNECT inputA[7] reg_A_reg_7_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_A_reg_7_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U67/Y reg_A_reg_7_/RN (0.000:0.000:0.000))
+    (INTERCONNECT inputA[6] reg_A_reg_6_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_A_reg_6_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U68/Y reg_A_reg_6_/RN (0.000:0.000:0.000))
+    (INTERCONNECT inputA[5] reg_A_reg_5_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_A_reg_5_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U68/Y reg_A_reg_5_/RN (0.000:0.000:0.000))
+    (INTERCONNECT inputB[0] reg_B_reg_0_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_B_reg_0_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U66/Y reg_B_reg_0_/RN (0.000:0.000:0.000))
+    (INTERCONNECT inputB[7] reg_B_reg_7_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_B_reg_7_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U67/Y reg_B_reg_7_/RN (0.000:0.000:0.000))
+    (INTERCONNECT inputA[0] reg_A_reg_0_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_A_reg_0_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U64/Y reg_A_reg_0_/RN (0.000:0.000:0.000))
+    (INTERCONNECT inputA[1] reg_A_reg_1_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_A_reg_1_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U64/Y reg_A_reg_1_/RN (0.000:0.000:0.000))
+    (INTERCONNECT inputA[2] reg_A_reg_2_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_A_reg_2_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U65/Y reg_A_reg_2_/RN (0.000:0.000:0.000))
+    (INTERCONNECT inputA[3] reg_A_reg_3_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_A_reg_3_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U66/Y reg_A_reg_3_/RN (0.000:0.000:0.000))
+    (INTERCONNECT inputB[1] reg_B_reg_1_/D (0.000:0.000:0.000))
+    (INTERCONNECT clk reg_B_reg_1_/CK (0.000:0.000:0.000))
+    (INTERCONNECT U64/Y reg_B_reg_1_/RN (0.000:0.000:0.000))
+    (INTERCONNECT U65/Y U68/A (0.000:0.000:0.000))
+    (INTERCONNECT U65/Y U67/A (0.000:0.000:0.000))
+    (INTERCONNECT reset U66/A (0.000:0.000:0.000))
+    (INTERCONNECT reset U65/A (0.000:0.000:0.000))
+    (INTERCONNECT reset U64/A (0.000:0.000:0.000))
+    (INTERCONNECT U31/Y U63/A (0.000:0.000:0.000))
+    (INTERCONNECT U53/Y U62/A (0.000:0.000:0.000))
+    (INTERCONNECT U17/Y U62/B (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_0_/Q U62/S0 (0.000:0.000:0.000))
+    (INTERCONNECT U53/Y U61/A (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_3_/QN U61/B (0.000:0.000:0.000))
+    (INTERCONNECT U3/Y U60/A (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_4_/QN U60/B (0.000:0.000:0.000))
+    (INTERCONNECT U3/Y U59/A (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_5_/QN U59/B (0.000:0.000:0.000))
+    (INTERCONNECT U3/Y U58/A (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_2_/QN U58/B (0.000:0.000:0.000))
+    (INTERCONNECT U3/Y U57/A (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_6_/QN U57/B (0.000:0.000:0.000))
+    (INTERCONNECT U53/Y U56/A (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_7_/QN U56/B (0.000:0.000:0.000))
+    (INTERCONNECT U53/Y U55/A (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_1_/QN U55/B (0.000:0.000:0.000))
+    (INTERCONNECT U53/Y U54/A (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_0_/QN U54/B (0.000:0.000:0.000))
+    (INTERCONNECT U31/Y U53/A (0.000:0.000:0.000))
+    (INTERCONNECT U51/Y U52/A (0.000:0.000:0.000))
+    (INTERCONNECT reg_ins_reg_3_/Q U51/A (0.000:0.000:0.000))
+    (INTERCONNECT reg_ins_reg_2_/Q U51/B (0.000:0.000:0.000))
+    (INTERCONNECT reg_ins_reg_1_/Q U51/C (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U1_6/S U50/A (0.000:0.000:0.000))
+    (INTERCONNECT U52/Y U50/B (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U1_0/S U49/A (0.000:0.000:0.000))
+    (INTERCONNECT U42/Y U49/B (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U1_1/S U48/A (0.000:0.000:0.000))
+    (INTERCONNECT U42/Y U48/B (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U1_7/Y U47/A (0.000:0.000:0.000))
+    (INTERCONNECT U52/Y U47/B (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U1_2/S U46/A (0.000:0.000:0.000))
+    (INTERCONNECT U52/Y U46/B (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U1_3/S U45/A (0.000:0.000:0.000))
+    (INTERCONNECT U52/Y U45/B (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U1_4/S U44/A (0.000:0.000:0.000))
+    (INTERCONNECT U52/Y U44/B (0.000:0.000:0.000))
+    (INTERCONNECT addsub/U1_5/S U43/A (0.000:0.000:0.000))
+    (INTERCONNECT U52/Y U43/B (0.000:0.000:0.000))
+    (INTERCONNECT U51/Y U42/A (0.000:0.000:0.000))
+    (INTERCONNECT reg_ins_reg_0_/Q U41/A (0.000:0.000:0.000))
+    (INTERCONNECT reg_ins_reg_1_/QN U41/B (0.000:0.000:0.000))
+    (INTERCONNECT reg_ins_reg_3_/Q U41/C (0.000:0.000:0.000))
+    (INTERCONNECT reg_ins_reg_2_/Q U41/D (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_6_/Q U40/A0 (0.000:0.000:0.000))
+    (INTERCONNECT U41/Y U40/A1 (0.000:0.000:0.000))
+    (INTERCONNECT U28/Y U40/B0 (0.000:0.000:0.000))
+    (INTERCONNECT U50/Y U40/C0 (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_0_/Q U39/A0 (0.000:0.000:0.000))
+    (INTERCONNECT U32/Y U39/A1 (0.000:0.000:0.000))
+    (INTERCONNECT U25/Y U39/B0 (0.000:0.000:0.000))
+    (INTERCONNECT U49/Y U39/C0 (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_1_/Q U38/A0 (0.000:0.000:0.000))
+    (INTERCONNECT U32/Y U38/A1 (0.000:0.000:0.000))
+    (INTERCONNECT U21/Y U38/B0 (0.000:0.000:0.000))
+    (INTERCONNECT U48/Y U38/C0 (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_7_/Q U37/A0 (0.000:0.000:0.000))
+    (INTERCONNECT U41/Y U37/A1 (0.000:0.000:0.000))
+    (INTERCONNECT U20/Y U37/B0 (0.000:0.000:0.000))
+    (INTERCONNECT U47/Y U37/C0 (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_2_/Q U36/A0 (0.000:0.000:0.000))
+    (INTERCONNECT U32/Y U36/A1 (0.000:0.000:0.000))
+    (INTERCONNECT U26/Y U36/B0 (0.000:0.000:0.000))
+    (INTERCONNECT U46/Y U36/C0 (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_3_/Q U35/A0 (0.000:0.000:0.000))
+    (INTERCONNECT U41/Y U35/A1 (0.000:0.000:0.000))
+    (INTERCONNECT U19/Y U35/B0 (0.000:0.000:0.000))
+    (INTERCONNECT U45/Y U35/C0 (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_4_/Q U34/A0 (0.000:0.000:0.000))
+    (INTERCONNECT U41/Y U34/A1 (0.000:0.000:0.000))
+    (INTERCONNECT U24/Y U34/B0 (0.000:0.000:0.000))
+    (INTERCONNECT U44/Y U34/C0 (0.000:0.000:0.000))
+    (INTERCONNECT reg_B_reg_5_/Q U33/A0 (0.000:0.000:0.000))
+    (INTERCONNECT U41/Y U33/A1 (0.000:0.000:0.000))
+    (INTERCONNECT U23/Y U33/B0 (0.000:0.000:0.000))
+    (INTERCONNECT U43/Y U33/C0 (0.000:0.000:0.000))
+    (INTERCONNECT U41/Y U32/A (0.000:0.000:0.000))
+    (INTERCONNECT reg_ins_reg_2_/Q U31/A (0.000:0.000:0.000))
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+    (COND B == 1'b1 && CI == 1'b0 (IOPATH A S (0.266:0.266:0.266) (0.299:0.299:0.299)))
+    (IOPATH A S (0.266:0.279:0.279) (0.293:0.299:0.299))
+    (COND A == 1'b0 && CI == 1'b0 (IOPATH B S (0.235:0.236:0.236) (0.228:0.232:0.232)))
+    (COND A == 1'b1 && CI == 1'b1 (IOPATH B S (0.233:0.234:0.234) (0.306:0.309:0.309)))
+    (COND A == 1'b0 && CI == 1'b1 (IOPATH B S (0.287:0.290:0.290) (0.249:0.249:0.249)))
+    (COND A == 1'b1 && CI == 1'b0 (IOPATH B S (0.272:0.275:0.275) (0.334:0.334:0.334)))
+    (IOPATH B S (0.287:0.293:0.293) (0.330:0.334:0.334))
+    (COND (A == 1'b0 && B == 1'b0) || (A == 1'b1 && B == 1'b1) (IOPATH CI S (0.110:0.113:0.113) (0.138:0.151:0.151)))
+    (COND (A == 1'b0 && B == 1'b1) || (A == 1'b1 && B == 1'b0) (IOPATH CI S (0.210:0.224:0.224) (0.151:0.154:0.154)))
+    (IOPATH CI S (0.210:0.224:0.224) (0.151:0.163:0.163))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "ADDFX2")
+  (INSTANCE addsub/U1_1)
+  (DELAY
+    (ABSOLUTE
+    (COND B == 1'b1 (IOPATH A CO (0.319:0.319:0.319) (0.279:0.279:0.279)))
+    (COND B == 1'b0 (IOPATH A CO (0.298:0.298:0.298) (0.279:0.279:0.279)))
+    (IOPATH A CO (0.319:0.319:0.319) (0.279:0.279:0.279))
+    (COND A == 1'b1 (IOPATH B CO (0.353:0.353:0.353) (0.191:0.194:0.194)))
+    (COND A == 1'b0 (IOPATH B CO (0.230:0.230:0.230) (0.306:0.309:0.309)))
+    (IOPATH B CO (0.353:0.353:0.353) (0.306:0.309:0.309))
+    (IOPATH CI CO (0.183:0.186:0.186) (0.189:0.201:0.201))
+    (COND B == 1'b0 && CI == 1'b0 (IOPATH A S (0.216:0.216:0.216) (0.226:0.226:0.226)))
+    (COND B == 1'b1 && CI == 1'b1 (IOPATH A S (0.214:0.214:0.214) (0.218:0.218:0.218)))
+    (COND B == 1'b0 && CI == 1'b1 (IOPATH A S (0.254:0.254:0.254) (0.268:0.268:0.268)))
+    (COND B == 1'b1 && CI == 1'b0 (IOPATH A S (0.266:0.266:0.266) (0.299:0.299:0.299)))
+    (IOPATH A S (0.266:0.279:0.279) (0.293:0.299:0.299))
+    (COND A == 1'b0 && CI == 1'b0 (IOPATH B S (0.235:0.236:0.236) (0.228:0.232:0.232)))
+    (COND A == 1'b1 && CI == 1'b1 (IOPATH B S (0.233:0.234:0.234) (0.306:0.309:0.309)))
+    (COND A == 1'b0 && CI == 1'b1 (IOPATH B S (0.287:0.290:0.290) (0.249:0.249:0.249)))
+    (COND A == 1'b1 && CI == 1'b0 (IOPATH B S (0.272:0.275:0.275) (0.334:0.334:0.334)))
+    (IOPATH B S (0.287:0.293:0.293) (0.330:0.334:0.334))
+    (COND (A == 1'b0 && B == 1'b0) || (A == 1'b1 && B == 1'b1) (IOPATH CI S (0.110:0.113:0.113) (0.138:0.151:0.151)))
+    (COND (A == 1'b0 && B == 1'b1) || (A == 1'b1 && B == 1'b0) (IOPATH CI S (0.210:0.224:0.224) (0.151:0.154:0.154)))
+    (IOPATH CI S (0.210:0.224:0.224) (0.151:0.163:0.163))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "ADDFX2")
+  (INSTANCE addsub/U1_6)
+  (DELAY
+    (ABSOLUTE
+    (COND B == 1'b1 (IOPATH A CO (0.323:0.323:0.323) (0.284:0.284:0.284)))
+    (COND B == 1'b0 (IOPATH A CO (0.303:0.303:0.303) (0.283:0.283:0.283)))
+    (IOPATH A CO (0.323:0.323:0.323) (0.284:0.284:0.284))
+    (COND A == 1'b1 (IOPATH B CO (0.358:0.358:0.358) (0.197:0.200:0.200)))
+    (COND A == 1'b0 (IOPATH B CO (0.235:0.235:0.235) (0.310:0.313:0.313)))
+    (IOPATH B CO (0.358:0.358:0.358) (0.310:0.313:0.313))
+    (IOPATH CI CO (0.188:0.190:0.190) (0.194:0.206:0.206))
+    (COND B == 1'b0 && CI == 1'b0 (IOPATH A S (0.216:0.216:0.216) (0.226:0.226:0.226)))
+    (COND B == 1'b1 && CI == 1'b1 (IOPATH A S (0.214:0.214:0.214) (0.218:0.218:0.218)))
+    (COND B == 1'b0 && CI == 1'b1 (IOPATH A S (0.254:0.254:0.254) (0.268:0.268:0.268)))
+    (COND B == 1'b1 && CI == 1'b0 (IOPATH A S (0.266:0.266:0.266) (0.299:0.299:0.299)))
+    (IOPATH A S (0.266:0.279:0.279) (0.293:0.299:0.299))
+    (COND A == 1'b0 && CI == 1'b0 (IOPATH B S (0.235:0.236:0.236) (0.228:0.232:0.232)))
+    (COND A == 1'b1 && CI == 1'b1 (IOPATH B S (0.233:0.234:0.234) (0.306:0.309:0.309)))
+    (COND A == 1'b0 && CI == 1'b1 (IOPATH B S (0.287:0.290:0.290) (0.249:0.249:0.249)))
+    (COND A == 1'b1 && CI == 1'b0 (IOPATH B S (0.272:0.275:0.275) (0.334:0.334:0.334)))
+    (IOPATH B S (0.287:0.293:0.293) (0.330:0.334:0.334))
+    (COND (A == 1'b0 && B == 1'b0) || (A == 1'b1 && B == 1'b1) (IOPATH CI S (0.110:0.113:0.113) (0.138:0.151:0.151)))
+    (COND (A == 1'b0 && B == 1'b1) || (A == 1'b1 && B == 1'b0) (IOPATH CI S (0.210:0.224:0.224) (0.151:0.154:0.154)))
+    (IOPATH CI S (0.210:0.224:0.224) (0.151:0.163:0.163))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "ADDFX2")
+  (INSTANCE addsub/U1_4)
+  (DELAY
+    (ABSOLUTE
+    (COND B == 1'b1 (IOPATH A CO (0.319:0.319:0.319) (0.279:0.279:0.279)))
+    (COND B == 1'b0 (IOPATH A CO (0.298:0.298:0.298) (0.279:0.279:0.279)))
+    (IOPATH A CO (0.319:0.319:0.319) (0.279:0.279:0.279))
+    (COND A == 1'b1 (IOPATH B CO (0.353:0.353:0.353) (0.191:0.194:0.194)))
+    (COND A == 1'b0 (IOPATH B CO (0.230:0.230:0.230) (0.306:0.309:0.309)))
+    (IOPATH B CO (0.353:0.353:0.353) (0.306:0.309:0.309))
+    (IOPATH CI CO (0.183:0.186:0.186) (0.189:0.201:0.201))
+    (COND B == 1'b0 && CI == 1'b0 (IOPATH A S (0.216:0.216:0.216) (0.226:0.226:0.226)))
+    (COND B == 1'b1 && CI == 1'b1 (IOPATH A S (0.214:0.214:0.214) (0.218:0.218:0.218)))
+    (COND B == 1'b0 && CI == 1'b1 (IOPATH A S (0.254:0.254:0.254) (0.268:0.268:0.268)))
+    (COND B == 1'b1 && CI == 1'b0 (IOPATH A S (0.266:0.266:0.266) (0.299:0.299:0.299)))
+    (IOPATH A S (0.266:0.279:0.279) (0.293:0.299:0.299))
+    (COND A == 1'b0 && CI == 1'b0 (IOPATH B S (0.235:0.236:0.236) (0.228:0.232:0.232)))
+    (COND A == 1'b1 && CI == 1'b1 (IOPATH B S (0.233:0.234:0.234) (0.306:0.309:0.309)))
+    (COND A == 1'b0 && CI == 1'b1 (IOPATH B S (0.287:0.290:0.290) (0.249:0.249:0.249)))
+    (COND A == 1'b1 && CI == 1'b0 (IOPATH B S (0.272:0.275:0.275) (0.334:0.334:0.334)))
+    (IOPATH B S (0.287:0.293:0.293) (0.330:0.334:0.334))
+    (COND (A == 1'b0 && B == 1'b0) || (A == 1'b1 && B == 1'b1) (IOPATH CI S (0.110:0.113:0.113) (0.138:0.151:0.151)))
+    (COND (A == 1'b0 && B == 1'b1) || (A == 1'b1 && B == 1'b0) (IOPATH CI S (0.210:0.224:0.224) (0.151:0.154:0.154)))
+    (IOPATH CI S (0.210:0.224:0.224) (0.151:0.163:0.163))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "ADDFX2")
+  (INSTANCE addsub/U1_2)
+  (DELAY
+    (ABSOLUTE
+    (COND B == 1'b1 (IOPATH A CO (0.319:0.319:0.319) (0.279:0.279:0.279)))
+    (COND B == 1'b0 (IOPATH A CO (0.298:0.298:0.298) (0.279:0.279:0.279)))
+    (IOPATH A CO (0.319:0.319:0.319) (0.279:0.279:0.279))
+    (COND A == 1'b1 (IOPATH B CO (0.353:0.353:0.353) (0.191:0.194:0.194)))
+    (COND A == 1'b0 (IOPATH B CO (0.230:0.230:0.230) (0.306:0.309:0.309)))
+    (IOPATH B CO (0.353:0.353:0.353) (0.306:0.309:0.309))
+    (IOPATH CI CO (0.183:0.186:0.186) (0.189:0.201:0.201))
+    (COND B == 1'b0 && CI == 1'b0 (IOPATH A S (0.216:0.216:0.216) (0.226:0.226:0.226)))
+    (COND B == 1'b1 && CI == 1'b1 (IOPATH A S (0.214:0.214:0.214) (0.218:0.218:0.218)))
+    (COND B == 1'b0 && CI == 1'b1 (IOPATH A S (0.254:0.254:0.254) (0.268:0.268:0.268)))
+    (COND B == 1'b1 && CI == 1'b0 (IOPATH A S (0.266:0.266:0.266) (0.299:0.299:0.299)))
+    (IOPATH A S (0.266:0.279:0.279) (0.293:0.299:0.299))
+    (COND A == 1'b0 && CI == 1'b0 (IOPATH B S (0.235:0.236:0.236) (0.228:0.232:0.232)))
+    (COND A == 1'b1 && CI == 1'b1 (IOPATH B S (0.233:0.234:0.234) (0.306:0.309:0.309)))
+    (COND A == 1'b0 && CI == 1'b1 (IOPATH B S (0.287:0.290:0.290) (0.249:0.249:0.249)))
+    (COND A == 1'b1 && CI == 1'b0 (IOPATH B S (0.272:0.275:0.275) (0.334:0.334:0.334)))
+    (IOPATH B S (0.287:0.293:0.293) (0.330:0.334:0.334))
+    (COND (A == 1'b0 && B == 1'b0) || (A == 1'b1 && B == 1'b1) (IOPATH CI S (0.110:0.113:0.113) (0.138:0.151:0.151)))
+    (COND (A == 1'b0 && B == 1'b1) || (A == 1'b1 && B == 1'b0) (IOPATH CI S (0.210:0.224:0.224) (0.151:0.154:0.154)))
+    (IOPATH CI S (0.210:0.224:0.224) (0.151:0.163:0.163))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "OR2X1")
+  (INSTANCE U69)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH A Y (0.205:0.205:0.205) (0.231:0.231:0.231))
+    (IOPATH B Y (0.211:0.211:0.211) (0.249:0.249:0.249))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "DFFRX1")
+  (INSTANCE reg_B_reg_2_)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH CK Q (0.463:0.463:0.463) (0.359:0.359:0.359))
+    (IOPATH RN Q () (0.298:0.298:0.298))
+    (IOPATH CK QN (0.256:0.256:0.256) (0.338:0.338:0.338))
+    (IOPATH RN QN (0.195:0.195:0.195) ())
+    )
+  )
+  (TIMINGCHECK
+    (WIDTH (posedge CK) (0.147:0.147:0.147))
+    (WIDTH (negedge CK) (0.176:0.176:0.176))
+    (SETUP D (posedge CK) (0.161:0.161:0.161))
+    (HOLD D (posedge CK) (-0.061:-0.038:-0.038))
+    (SETUP RN (posedge CK) (0.071:0.071:0.071))
+    (HOLD RN (posedge CK) (-0.043:-0.043:-0.043))
+    (WIDTH (negedge RN) (0.195:0.195:0.195))
+  )
+)
+(CELL
+  (CELLTYPE "DFFRX1")
+  (INSTANCE reg_B_reg_3_)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH CK Q (0.463:0.463:0.463) (0.359:0.359:0.359))
+    (IOPATH RN Q () (0.296:0.296:0.296))
+    (IOPATH CK QN (0.256:0.256:0.256) (0.338:0.338:0.338))
+    (IOPATH RN QN (0.193:0.193:0.193) ())
+    )
+  )
+  (TIMINGCHECK
+    (WIDTH (posedge CK) (0.147:0.147:0.147))
+    (WIDTH (negedge CK) (0.176:0.176:0.176))
+    (SETUP D (posedge CK) (0.161:0.161:0.161))
+    (HOLD D (posedge CK) (-0.061:-0.038:-0.038))
+    (SETUP RN (posedge CK) (0.070:0.070:0.070))
+    (HOLD RN (posedge CK) (-0.042:-0.042:-0.042))
+    (WIDTH (negedge RN) (0.195:0.195:0.195))
+  )
+)
+(CELL
+  (CELLTYPE "DFFRX1")
+  (INSTANCE reg_B_reg_4_)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH CK Q (0.463:0.463:0.463) (0.359:0.359:0.359))
+    (IOPATH RN Q () (0.298:0.298:0.298))
+    (IOPATH CK QN (0.256:0.256:0.256) (0.338:0.338:0.338))
+    (IOPATH RN QN (0.195:0.195:0.195) ())
+    )
+  )
+  (TIMINGCHECK
+    (WIDTH (posedge CK) (0.147:0.147:0.147))
+    (WIDTH (negedge CK) (0.176:0.176:0.176))
+    (SETUP D (posedge CK) (0.161:0.161:0.161))
+    (HOLD D (posedge CK) (-0.061:-0.038:-0.038))
+    (SETUP RN (posedge CK) (0.070:0.070:0.070))
+    (HOLD RN (posedge CK) (-0.043:-0.043:-0.043))
+    (WIDTH (negedge RN) (0.195:0.195:0.195))
+  )
+)
+(CELL
+  (CELLTYPE "DFFRX1")
+  (INSTANCE reg_B_reg_5_)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH CK Q (0.463:0.463:0.463) (0.359:0.359:0.359))
+    (IOPATH RN Q () (0.298:0.298:0.298))
+    (IOPATH CK QN (0.256:0.256:0.256) (0.338:0.338:0.338))
+    (IOPATH RN QN (0.195:0.195:0.195) ())
+    )
+  )
+  (TIMINGCHECK
+    (WIDTH (posedge CK) (0.147:0.147:0.147))
+    (WIDTH (negedge CK) (0.176:0.176:0.176))
+    (SETUP D (posedge CK) (0.161:0.161:0.161))
+    (HOLD D (posedge CK) (-0.061:-0.038:-0.038))
+    (SETUP RN (posedge CK) (0.070:0.070:0.070))
+    (HOLD RN (posedge CK) (-0.043:-0.043:-0.043))
+    (WIDTH (negedge RN) (0.195:0.195:0.195))
+  )
+)
+(CELL
+  (CELLTYPE "DFFRX1")
+  (INSTANCE reg_B_reg_6_)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH CK Q (0.463:0.463:0.463) (0.359:0.359:0.359))
+    (IOPATH RN Q () (0.298:0.298:0.298))
+    (IOPATH CK QN (0.256:0.256:0.256) (0.338:0.338:0.338))
+    (IOPATH RN QN (0.195:0.195:0.195) ())
+    )
+  )
+  (TIMINGCHECK
+    (WIDTH (posedge CK) (0.147:0.147:0.147))
+    (WIDTH (negedge CK) (0.176:0.176:0.176))
+    (SETUP D (posedge CK) (0.161:0.161:0.161))
+    (HOLD D (posedge CK) (-0.061:-0.038:-0.038))
+    (SETUP RN (posedge CK) (0.070:0.070:0.070))
+    (HOLD RN (posedge CK) (-0.043:-0.043:-0.043))
+    (WIDTH (negedge RN) (0.195:0.195:0.195))
+  )
+)
+(CELL
+  (CELLTYPE "DFFRX1")
+  (INSTANCE reg_ins_reg_3_)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH CK Q (0.461:0.461:0.461) (0.358:0.358:0.358))
+    (IOPATH RN Q () (0.295:0.295:0.295))
+    (IOPATH CK QN (0.244:0.244:0.244) (0.327:0.327:0.327))
+    (IOPATH RN QN (0.182:0.182:0.182) ())
+    )
+  )
+  (TIMINGCHECK
+    (WIDTH (posedge CK) (0.147:0.147:0.147))
+    (WIDTH (negedge CK) (0.176:0.176:0.176))
+    (SETUP D (posedge CK) (0.161:0.161:0.161))
+    (HOLD D (posedge CK) (-0.061:-0.038:-0.038))
+    (SETUP RN (posedge CK) (0.070:0.070:0.070))
+    (HOLD RN (posedge CK) (-0.042:-0.042:-0.042))
+    (WIDTH (negedge RN) (0.195:0.195:0.195))
+  )
+)
+(CELL
+  (CELLTYPE "DFFRX1")
+  (INSTANCE reg_ins_reg_2_)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH CK Q (0.442:0.442:0.442) (0.345:0.345:0.345))
+    (IOPATH RN Q () (0.284:0.284:0.284))
+    (IOPATH CK QN (0.263:0.263:0.263) (0.344:0.344:0.344))
+    (IOPATH RN QN (0.202:0.202:0.202) ())
+    )
+  )
+  (TIMINGCHECK
+    (WIDTH (posedge CK) (0.147:0.147:0.147))
+    (WIDTH (negedge CK) (0.176:0.176:0.176))
+    (SETUP D (posedge CK) (0.161:0.161:0.161))
+    (HOLD D (posedge CK) (-0.061:-0.038:-0.038))
+    (SETUP RN (posedge CK) (0.071:0.071:0.071))
+    (HOLD RN (posedge CK) (-0.043:-0.043:-0.043))
+    (WIDTH (negedge RN) (0.195:0.195:0.195))
+  )
+)
+(CELL
+  (CELLTYPE "DFFRX1")
+  (INSTANCE reg_ins_reg_1_)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH CK Q (0.414:0.414:0.414) (0.324:0.324:0.324))
+    (IOPATH RN Q () (0.261:0.261:0.261))
+    (IOPATH CK QN (0.281:0.281:0.281) (0.361:0.361:0.361))
+    (IOPATH RN QN (0.219:0.219:0.219) ())
+    )
+  )
+  (TIMINGCHECK
+    (WIDTH (posedge CK) (0.147:0.147:0.147))
+    (WIDTH (negedge CK) (0.176:0.176:0.176))
+    (SETUP D (posedge CK) (0.161:0.161:0.161))
+    (HOLD D (posedge CK) (-0.061:-0.038:-0.038))
+    (SETUP RN (posedge CK) (0.070:0.070:0.070))
+    (HOLD RN (posedge CK) (-0.042:-0.042:-0.042))
+    (WIDTH (negedge RN) (0.195:0.195:0.195))
+  )
+)
+(CELL
+  (CELLTYPE "DFFRX1")
+  (INSTANCE reg_ins_reg_0_)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH CK Q (0.429:0.429:0.429) (0.335:0.335:0.335))
+    (IOPATH RN Q () (0.259:0.259:0.259))
+    (IOPATH CK QN (0.263:0.263:0.263) (0.345:0.345:0.345))
+    (IOPATH RN QN (0.187:0.187:0.187) ())
+    )
+  )
+  (TIMINGCHECK
+    (WIDTH (posedge CK) (0.147:0.147:0.147))
+    (WIDTH (negedge CK) (0.176:0.176:0.176))
+    (SETUP D (posedge CK) (0.161:0.161:0.161))
+    (HOLD D (posedge CK) (-0.061:-0.038:-0.038))
+    (SETUP RN (posedge CK) (0.067:0.067:0.067))
+    (HOLD RN (posedge CK) (-0.039:-0.039:-0.039))
+    (WIDTH (negedge RN) (0.195:0.195:0.195))
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+    (IOPATH RN QN (0.183:0.183:0.183) ())
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+    (IOPATH RN QN (0.183:0.183:0.183) ())
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+    (IOPATH RN QN (0.184:0.184:0.184) ())
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+    (IOPATH RN QN (0.183:0.183:0.183) ())
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+    (IOPATH RN QN (0.193:0.193:0.193) ())
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+    (COND A == 1'b1 && B == 1'b0 (IOPATH S0 Y (0.154:0.154:0.154) (0.129:0.129:0.129)))
+    (COND A == 1'b0 && B == 1'b1 (IOPATH S0 Y (0.090:0.090:0.090) (0.114:0.114:0.114)))
+    (IOPATH S0 Y (0.154:0.173:0.173) (0.116:0.131:0.131))
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+  (INSTANCE U14)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH A Y (0.111:0.111:0.111) (0.126:0.127:0.127))
+    (IOPATH B Y (0.119:0.119:0.119) (0.139:0.139:0.139))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "MX2X2")
+  (INSTANCE U13)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH A Y (0.106:0.106:0.106) (0.118:0.118:0.118))
+    (IOPATH B Y (0.108:0.108:0.108) (0.134:0.134:0.134))
+    (COND A == 1'b1 && B == 1'b0 (IOPATH S0 Y (0.154:0.154:0.154) (0.129:0.129:0.129)))
+    (COND A == 1'b0 && B == 1'b1 (IOPATH S0 Y (0.090:0.090:0.090) (0.114:0.114:0.114)))
+    (IOPATH S0 Y (0.154:0.173:0.173) (0.116:0.131:0.131))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "AND2X1")
+  (INSTANCE U12)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH A Y (0.111:0.111:0.111) (0.126:0.127:0.127))
+    (IOPATH B Y (0.119:0.119:0.119) (0.139:0.139:0.139))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "MX2X2")
+  (INSTANCE U11)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH A Y (0.107:0.107:0.107) (0.118:0.118:0.118))
+    (IOPATH B Y (0.108:0.108:0.108) (0.134:0.134:0.134))
+    (COND A == 1'b1 && B == 1'b0 (IOPATH S0 Y (0.154:0.154:0.154) (0.129:0.129:0.129)))
+    (COND A == 1'b0 && B == 1'b1 (IOPATH S0 Y (0.090:0.090:0.090) (0.114:0.114:0.114)))
+    (IOPATH S0 Y (0.154:0.173:0.173) (0.116:0.131:0.131))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "MX2X2")
+  (INSTANCE U10)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH A Y (0.107:0.107:0.107) (0.118:0.118:0.118))
+    (IOPATH B Y (0.108:0.108:0.108) (0.134:0.134:0.134))
+    (COND A == 1'b1 && B == 1'b0 (IOPATH S0 Y (0.154:0.154:0.154) (0.129:0.129:0.129)))
+    (COND A == 1'b0 && B == 1'b1 (IOPATH S0 Y (0.090:0.090:0.090) (0.114:0.114:0.114)))
+    (IOPATH S0 Y (0.154:0.173:0.173) (0.116:0.131:0.131))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "MX2X2")
+  (INSTANCE U9)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH A Y (0.107:0.107:0.107) (0.118:0.118:0.118))
+    (IOPATH B Y (0.108:0.108:0.108) (0.134:0.134:0.134))
+    (COND A == 1'b1 && B == 1'b0 (IOPATH S0 Y (0.154:0.154:0.154) (0.129:0.129:0.129)))
+    (COND A == 1'b0 && B == 1'b1 (IOPATH S0 Y (0.090:0.090:0.090) (0.114:0.114:0.114)))
+    (IOPATH S0 Y (0.154:0.173:0.173) (0.116:0.131:0.131))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "AND2X1")
+  (INSTANCE U8)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH A Y (0.111:0.111:0.111) (0.126:0.127:0.127))
+    (IOPATH B Y (0.122:0.122:0.122) (0.152:0.152:0.152))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "AND2X1")
+  (INSTANCE U7)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH A Y (0.111:0.111:0.111) (0.126:0.127:0.127))
+    (IOPATH B Y (0.122:0.122:0.122) (0.152:0.152:0.152))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "AND2X1")
+  (INSTANCE U6)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH A Y (0.111:0.111:0.111) (0.126:0.127:0.127))
+    (IOPATH B Y (0.122:0.122:0.122) (0.152:0.152:0.152))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "AND2X1")
+  (INSTANCE U5)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH A Y (0.111:0.111:0.111) (0.126:0.127:0.127))
+    (IOPATH B Y (0.122:0.122:0.122) (0.152:0.152:0.152))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "AND2X1")
+  (INSTANCE U4)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH A Y (0.111:0.111:0.111) (0.126:0.127:0.127))
+    (IOPATH B Y (0.122:0.122:0.122) (0.152:0.152:0.152))
+    )
+  )
+)
+(CELL
+  (CELLTYPE "INVX2")
+  (INSTANCE U3)
+  (DELAY
+    (ABSOLUTE
+    (IOPATH A Y (0.096:0.096:0.096) (0.068:0.068:0.068))
+    )
+  )
+)
+)

lab2/Lab2_alu_s.v

@@ -0,0 +1,167 @@
+
+module ALU_DW01_addsub_8_0 ( A, B, CI, ADD_SUB, SUM, CO );
+  input [7:0] A;
+  input [7:0] B;
+  output [7:0] SUM;
+  input CI, ADD_SUB;
+  output CO;
+  wire   \carry[7] , \carry[6] , \carry[5] , \carry[4] , \carry[3] ,
+         \carry[2] , \carry[1] , \carry[0] ;
+  wire   [7:0] B_AS;
+
+  ADDFX2 U1_2 ( .A(A[2]), .B(B_AS[2]), .CI(\carry[2] ), .S(SUM[2]), .CO(
+        \carry[3] ) );
+  ADDFX2 U1_4 ( .A(A[4]), .B(B_AS[4]), .CI(\carry[4] ), .S(SUM[4]), .CO(
+        \carry[5] ) );
+  ADDFX2 U1_6 ( .A(A[6]), .B(B_AS[6]), .CI(\carry[6] ), .S(SUM[6]), .CO(
+        \carry[7] ) );
+  ADDFX2 U1_1 ( .A(A[1]), .B(B_AS[1]), .CI(\carry[1] ), .S(SUM[1]), .CO(
+        \carry[2] ) );
+  ADDFX2 U1_3 ( .A(A[3]), .B(B_AS[3]), .CI(\carry[3] ), .S(SUM[3]), .CO(
+        \carry[4] ) );
+  ADDFX2 U1_5 ( .A(A[5]), .B(B_AS[5]), .CI(\carry[5] ), .S(SUM[5]), .CO(
+        \carry[6] ) );
+  XOR3X2 U1_7 ( .A(A[7]), .B(B_AS[7]), .C(\carry[7] ), .Y(SUM[7]) );
+  XOR2X1 U4 ( .A(B[7]), .B(ADD_SUB), .Y(B_AS[7]) );
+  XOR2X1 U5 ( .A(B[6]), .B(ADD_SUB), .Y(B_AS[6]) );
+  XOR2X1 U6 ( .A(B[5]), .B(ADD_SUB), .Y(B_AS[5]) );
+  XOR2X1 U7 ( .A(B[4]), .B(ADD_SUB), .Y(B_AS[4]) );
+  XOR2X1 U8 ( .A(B[3]), .B(\carry[0] ), .Y(B_AS[3]) );
+  XOR2X1 U9 ( .A(B[2]), .B(\carry[0] ), .Y(B_AS[2]) );
+  ADDFX2 U1_0 ( .A(A[0]), .B(B_AS[0]), .CI(\carry[0] ), .S(SUM[0]), .CO(
+        \carry[1] ) );
+  XOR2X1 U10 ( .A(B[1]), .B(\carry[0] ), .Y(B_AS[1]) );
+  XOR2X1 U11 ( .A(B[0]), .B(\carry[0] ), .Y(B_AS[0]) );
+  BUFX2 U12 ( .A(ADD_SUB), .Y(\carry[0] ) );
+endmodule
+
+
+module ALU ( alu_out, instruction, inputA, inputB, clk, reset );
+  output [7:0] alu_out;
+  input [3:0] instruction;
+  input [7:0] inputA;
+  input [7:0] inputB;
+  input clk, reset;
+  wire   add_sub, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64,
+         n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78,
+         n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92,
+         n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
+         n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116,
+         n117, n118, n119, n120, n121;
+  wire   [7:0] reg_A;
+  wire   [7:0] reg_B;
+  wire   [7:0] sum;
+  wire   [3:0] reg_ins;
+  wire   [7:0] X;
+
+  INVX2 U3 ( .A(n53), .Y(n120) );
+  AND2X1 U4 ( .A(n95), .B(n70), .Y(n94) );
+  AND2X1 U5 ( .A(n69), .B(n70), .Y(n68) );
+  AND2X1 U6 ( .A(n107), .B(n70), .Y(n106) );
+  AND2X1 U7 ( .A(n89), .B(n70), .Y(n88) );
+  AND2X1 U8 ( .A(n101), .B(n70), .Y(n100) );
+  MX2X2 U9 ( .S0(reg_B[7]), .B(n71), .A(n121), .Y(n69) );
+  MX2X2 U10 ( .S0(reg_B[3]), .B(n71), .A(n121), .Y(n95) );
+  MX2X2 U11 ( .S0(reg_B[1]), .B(n71), .A(n121), .Y(n107) );
+  AND2X1 U12 ( .A(n83), .B(n119), .Y(n82) );
+  MX2X2 U13 ( .S0(reg_B[4]), .B(n71), .A(n56), .Y(n89) );
+  AND2X1 U14 ( .A(n113), .B(n119), .Y(n112) );
+  MX2X2 U15 ( .S0(reg_B[2]), .B(n71), .A(n120), .Y(n101) );
+  AND2X1 U16 ( .A(n77), .B(n119), .Y(n76) );
+  BUFX2 U17 ( .A(n71), .Y(n118) );
+  OR4X2 U18 ( .A(reg_ins[0]), .B(n114), .C(reg_ins[3]), .D(reg_ins[1]), .Y(n70) );
+  MX2X2 U19 ( .S0(reg_A[3]), .B(n94), .A(n93), .Y(n91) );
+  MX2X2 U20 ( .S0(reg_A[7]), .B(n68), .A(n67), .Y(n64) );
+  MX2X2 U21 ( .S0(reg_A[1]), .B(n106), .A(n105), .Y(n103) );
+  MX2X2 U22 ( .S0(reg_B[5]), .B(n118), .A(n121), .Y(n83) );
+  MX2X2 U23 ( .S0(reg_A[5]), .B(n82), .A(n81), .Y(n79) );
+  MX2X2 U24 ( .S0(reg_A[4]), .B(n88), .A(n87), .Y(n85) );
+  MX2X2 U25 ( .S0(reg_A[0]), .B(n112), .A(n111), .Y(n109) );
+  MX2X2 U26 ( .S0(reg_A[2]), .B(n100), .A(n99), .Y(n97) );
+  MX2X2 U27 ( .S0(reg_B[6]), .B(n118), .A(n120), .Y(n77) );
+  MX2X2 U28 ( .S0(reg_A[6]), .B(n76), .A(n75), .Y(n73) );
+  OR4X2 U29 ( .A(n115), .B(n116), .C(reg_ins[3]), .D(reg_ins[2]), .Y(n71) );
+  BUFX2 U30 ( .A(n70), .Y(n119) );
+  OR2XL U31 ( .A(reg_ins[2]), .B(reg_ins[3]), .Y(n53) );
+  BUFX2 U32 ( .A(n63), .Y(n54) );
+  OAI211X1 U33 ( .A0(reg_B[5]), .A1(n63), .B0(n79), .C0(n80), .Y(X[5]) );
+  OAI211X1 U34 ( .A0(reg_B[4]), .A1(n63), .B0(n85), .C0(n86), .Y(X[4]) );
+  OAI211X1 U35 ( .A0(reg_B[3]), .A1(n63), .B0(n91), .C0(n92), .Y(X[3]) );
+  OAI211X1 U36 ( .A0(reg_B[2]), .A1(n54), .B0(n97), .C0(n98), .Y(X[2]) );
+  OAI211X1 U37 ( .A0(reg_B[7]), .A1(n63), .B0(n64), .C0(n65), .Y(X[7]) );
+  OAI211X1 U38 ( .A0(reg_B[1]), .A1(n54), .B0(n103), .C0(n104), .Y(X[1]) );
+  OAI211X1 U39 ( .A0(reg_B[0]), .A1(n54), .B0(n109), .C0(n110), .Y(X[0]) );
+  OAI211X1 U40 ( .A0(reg_B[6]), .A1(n63), .B0(n73), .C0(n74), .Y(X[6]) );
+  OR4X2 U41 ( .A(reg_ins[0]), .B(n116), .C(reg_ins[3]), .D(reg_ins[2]), .Y(n63) );
+  INVX2 U42 ( .A(n62), .Y(n55) );
+  NAND2X1 U43 ( .A(sum[5]), .B(n66), .Y(n80) );
+  NAND2X1 U44 ( .A(sum[4]), .B(n66), .Y(n86) );
+  NAND2X1 U45 ( .A(sum[3]), .B(n66), .Y(n92) );
+  NAND2X1 U46 ( .A(sum[2]), .B(n66), .Y(n98) );
+  NAND2X1 U47 ( .A(sum[7]), .B(n66), .Y(n65) );
+  NAND2X1 U48 ( .A(sum[1]), .B(n55), .Y(n104) );
+  NAND2X1 U49 ( .A(sum[0]), .B(n55), .Y(n110) );
+  NAND2X1 U50 ( .A(sum[6]), .B(n66), .Y(n74) );
+  OR3X2 U51 ( .A(reg_ins[3]), .B(reg_ins[2]), .C(reg_ins[1]), .Y(n62) );
+  INVX2 U52 ( .A(n62), .Y(n66) );
+  INVX2 U53 ( .A(n53), .Y(n56) );
+  OR2X1 U54 ( .A(n56), .B(n117), .Y(n111) );
+  OR2X1 U55 ( .A(n56), .B(n108), .Y(n105) );
+  OR2X1 U56 ( .A(n56), .B(n72), .Y(n67) );
+  OR2X1 U57 ( .A(n120), .B(n78), .Y(n75) );
+  OR2X1 U58 ( .A(n120), .B(n102), .Y(n99) );
+  OR2X1 U59 ( .A(n120), .B(n84), .Y(n81) );
+  OR2X1 U60 ( .A(n120), .B(n90), .Y(n87) );
+  OR2X1 U61 ( .A(n56), .B(n96), .Y(n93) );
+  MX2X2 U62 ( .S0(reg_B[0]), .B(n118), .A(n56), .Y(n113) );
+  INVX2 U63 ( .A(n53), .Y(n121) );
+  BUFX2 U64 ( .A(reset), .Y(n57) );
+  BUFX2 U65 ( .A(reset), .Y(n58) );
+  BUFX2 U66 ( .A(reset), .Y(n59) );
+  BUFX2 U67 ( .A(n58), .Y(n60) );
+  BUFX2 U68 ( .A(n58), .Y(n61) );
+  DFFRX1 reg_B_reg_1_ ( .D(inputB[1]), .CK(clk), .RN(n57), .Q(reg_B[1]), .QN(
+        n108) );
+  DFFRX1 reg_A_reg_3_ ( .D(inputA[3]), .CK(clk), .RN(n59), .Q(reg_A[3]) );
+  DFFRX1 reg_A_reg_2_ ( .D(inputA[2]), .CK(clk), .RN(n58), .Q(reg_A[2]) );
+  DFFRX1 reg_A_reg_1_ ( .D(inputA[1]), .CK(clk), .RN(n57), .Q(reg_A[1]) );
+  DFFRX1 reg_A_reg_0_ ( .D(inputA[0]), .CK(clk), .RN(n57), .Q(reg_A[0]) );
+  DFFRX1 reg_B_reg_7_ ( .D(inputB[7]), .CK(clk), .RN(n60), .Q(reg_B[7]), .QN(
+        n72) );
+  DFFRX1 reg_B_reg_0_ ( .D(inputB[0]), .CK(clk), .RN(n59), .Q(reg_B[0]), .QN(
+        n117) );
+  DFFRX1 reg_A_reg_5_ ( .D(inputA[5]), .CK(clk), .RN(n61), .Q(reg_A[5]) );
+  DFFRX1 reg_A_reg_6_ ( .D(inputA[6]), .CK(clk), .RN(n61), .Q(reg_A[6]) );
+  DFFRX1 reg_A_reg_7_ ( .D(inputA[7]), .CK(clk), .RN(n60), .Q(reg_A[7]) );
+  DFFRX1 alu_out_reg_0_ ( .D(X[0]), .CK(clk), .RN(reset), .Q(alu_out[0]) );
+  DFFRX1 alu_out_reg_1_ ( .D(X[1]), .CK(clk), .RN(n57), .Q(alu_out[1]) );
+  DFFRX1 alu_out_reg_2_ ( .D(X[2]), .CK(clk), .RN(n58), .Q(alu_out[2]) );
+  DFFRX1 alu_out_reg_3_ ( .D(X[3]), .CK(clk), .RN(n59), .Q(alu_out[3]) );
+  DFFRX1 reg_A_reg_4_ ( .D(inputA[4]), .CK(clk), .RN(n60), .Q(reg_A[4]) );
+  DFFRX1 alu_out_reg_4_ ( .D(X[4]), .CK(clk), .RN(n60), .Q(alu_out[4]) );
+  DFFRX1 alu_out_reg_5_ ( .D(X[5]), .CK(clk), .RN(n61), .Q(alu_out[5]) );
+  DFFRX1 alu_out_reg_6_ ( .D(X[6]), .CK(clk), .RN(n61), .Q(alu_out[6]) );
+  DFFRX1 alu_out_reg_7_ ( .D(X[7]), .CK(clk), .RN(n60), .Q(alu_out[7]) );
+  DFFRX1 reg_ins_reg_0_ ( .D(instruction[0]), .CK(clk), .RN(reset), .Q(
+        reg_ins[0]), .QN(n115) );
+  DFFRX1 reg_ins_reg_1_ ( .D(instruction[1]), .CK(clk), .RN(n57), .Q(
+        reg_ins[1]), .QN(n116) );
+  DFFRX1 reg_ins_reg_2_ ( .D(instruction[2]), .CK(clk), .RN(n58), .Q(
+        reg_ins[2]), .QN(n114) );
+  DFFRX1 reg_ins_reg_3_ ( .D(instruction[3]), .CK(clk), .RN(n59), .Q(
+        reg_ins[3]) );
+  DFFRX1 reg_B_reg_6_ ( .D(inputB[6]), .CK(clk), .RN(n61), .Q(reg_B[6]), .QN(
+        n78) );
+  DFFRX1 reg_B_reg_5_ ( .D(inputB[5]), .CK(clk), .RN(n61), .Q(reg_B[5]), .QN(
+        n84) );
+  DFFRX1 reg_B_reg_4_ ( .D(inputB[4]), .CK(clk), .RN(n60), .Q(reg_B[4]), .QN(
+        n90) );
+  DFFRX1 reg_B_reg_3_ ( .D(inputB[3]), .CK(clk), .RN(n59), .Q(reg_B[3]), .QN(
+        n96) );
+  DFFRX1 reg_B_reg_2_ ( .D(inputB[2]), .CK(clk), .RN(n58), .Q(reg_B[2]), .QN(
+        n102) );
+  OR2X1 U69 ( .A(reg_ins[0]), .B(n62), .Y(add_sub) );
+  ALU_DW01_addsub_8_0 addsub ( .A(reg_A), .B(reg_B), .CI(1'b0), .ADD_SUB(
+        add_sub), .SUM(sum) );
+endmodule
+

lab2/Lab2_test_alu.v

@@ -0,0 +1,135 @@
+`timescale 1ns/100ps
+
+module test_alu;
+reg [7:0] inputA,inputB,true_out;
+reg clk,reset;
+reg [3:0] instruction;
+wire [7:0] alu_out;
+
+integer i,j,outfile,pat_error;
+
+  ALU my_alu(alu_out,instruction,inputA,inputB,clk,reset);
+
+always #5 clk=~clk;                      //cycle time is 10ns
+
+initial begin
+  //$dumpfile("Lab2_alu.vcd");
+  //$dumpvars;
+  //$sdf_annotate("Lab2_alu_s.sdf",my_alu);
+  //$fsdbDumpfile("Lab2_alu.fsdb"); 
+  //$fsdbDumpvars;  
+  outfile=$fopen("alu_out.txt");          //open one file for writing
+  if(!outfile) begin
+    $display("Can not write file!");
+    $finish;
+  end
+
+  pat_error=0;
+
+  reset=1'b1;clk=1'b1;inputA=0;inputB=0;instruction=0;
+  #2 reset=1'b0;                            // system reset
+  #3 reset=1'b1;
+     // test for instruction 0: Add
+     instruction=0;
+     for(i=0;i<256;i=i+1)
+     begin
+       for(j=0;j<256;j=j+1)
+       begin
+         inputA=i[7:0];inputB=j[7:0];
+         #20  true_out=inputA+inputB;
+             if(alu_out !== true_out[7:0]) 
+             begin
+               $fdisplay(outfile,"%b + %b should be %b. But your output is %b.",inputA,inputB,true_out,alu_out);
+               pat_error=pat_error+1;
+             end                           
+       end
+     end
+     
+     // test for instruction 1: Sub
+     instruction=4'b0001;
+     for(i=0;i<256;i=i+1)
+     begin
+       for(j=0;j<256;j=j+1)
+       begin
+         inputA=i[7:0];inputB=j[7:0];
+         #20 true_out=inputA-inputB;
+             if(alu_out !== true_out[7:0]) 
+             begin
+               $fdisplay(outfile,"%b - %b should be %b. But your output is %b.",inputA,inputB,true_out,alu_out);
+               pat_error=pat_error+1;
+             end                           
+       end
+     end
+
+     // test for instruction 2: Not
+     instruction=4'b0010;
+       for(j=0;j<256;j=j+1)
+       begin
+         inputB=j[7:0];
+         #20 true_out=~inputB;
+             if(alu_out !== true_out[7:0]) 
+             begin
+               $fdisplay(outfile,"~ %b should be %b. But your output is %b.",inputB,true_out,alu_out);
+               pat_error=pat_error+1;
+             end                           
+       end
+  
+     // test for instruction 3: And
+     instruction=4'b0011;
+     for(i=0;i<256;i=i+1)
+     begin
+       for(j=0;j<256;j=j+1)
+       begin
+         inputA=i[7:0];inputB=j[7:0];
+         #20 true_out=inputA&inputB;
+             if(alu_out !== true_out[7:0]) 
+             begin
+               $fdisplay(outfile,"%b & %b should be %b. But your output is %b.",inputA,inputB,true_out,alu_out);
+               pat_error=pat_error+1;
+             end                           
+       end
+     end  
+
+     // test for instruction 4: Or
+     instruction=4'b0100;
+     for(i=0;i<256;i=i+1)
+     begin
+       for(j=0;j<256;j=j+1)
+       begin
+         inputA=i[7:0];inputB=j[7:0];
+         #20 true_out=inputA|inputB;
+             if(alu_out !== true_out[7:0]) 
+             begin
+               $fdisplay(outfile,"%b | %b should be %b. But your output is %b.",inputA,inputB,true_out,alu_out);
+               pat_error=pat_error+1;
+             end                           
+       end
+     end
+
+     // test for instruction 5: Xor
+     instruction=4'b0101;
+     for(i=0;i<256;i=i+1)
+     begin
+       for(j=0;j<256;j=j+1)
+       begin
+         inputA=i[7:0];inputB=j[7:0];
+         #20 true_out=inputA^inputB;
+             if(alu_out !== true_out[7:0]) 
+             begin
+               $fdisplay(outfile,"%b ^ %b should be %b. But your output is %b.",inputA,inputB,true_out,alu_out);
+               pat_error=pat_error+1;
+             end                           
+       end
+     end
+          
+     if(!pat_error)
+       $display("\nCongratulations!! Your Verilog Code is correct!!\n");
+     else
+       $display("\nYour Verilog Code has %d errors. \nPlease read alu_out.txt for details.\n",pat_error);
+  #10 $finish;
+  
+
+
+end
+
+endmodule

lab2/Lab2_test_ram.v

@@ -0,0 +1,64 @@
+`timescale 1ns/100fs
+
+module test_ram;
+reg [5:0] Addr;
+reg [7:0] I;
+reg WEB,OEB,CEB,clk;
+wire [7:0] O;
+
+integer i,j,outfile,pat_error;
+
+HSs13n_512x8 my_ram(.A(Addr),
+                   .D(I),
+                   .CLK(~clk),
+                   .CEN(CEB),
+                   .WEN(WEB),
+                   .Q(O) );
+
+always #10 clk=~clk;                      //cycle time is 20ns
+
+initial begin
+  $fsdbDumpfile("Lab2_ram.fsdb"); 
+  $fsdbDumpvars;  
+  outfile=$fopen("ram_out.txt");          //open one file for writing
+  if(!outfile) begin
+    $display("Can not write file!");
+    $finish;
+  end
+
+  pat_error=0;
+
+  clk=1'b1;CEB=1'b1;WEB=1'b1;OEB=1'b0;I=0;Addr=0;
+  #5 // Memory Write
+     for(i=0;i<64;i=i+1)
+     begin
+         CEB=1'b0;WEB=1'b0;OEB=1'b0;Addr=i[5:0];
+         j=i*i;
+         I=j[7:0];
+         #20 ;                          
+     end
+     
+     // Memory Read
+     for(i=0;i<64;i=i+1)
+     begin
+         CEB=1'b0;WEB=1'b1;OEB=1'b0;Addr=i[5:0];
+         #20 j=i*i;
+             if(O[7:0] !== j[7:0]) 
+             begin
+               $fdisplay(outfile,"Memory content of Address %b should be %b. But your output is %b.",Addr,j[7:0],O);
+               pat_error=pat_error+1;
+             end                           
+     end
+
+          
+     if(!pat_error)
+       $display("\nCongratulations!! Your RAM Controller is correct!!\n");
+     else
+       $display("\nYour RAM Controller has %d errors. \nPlease read ram_out.txt for details.\n",pat_error);
+  #10 $finish;
+  
+
+
+end
+
+endmodule